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1 ltc1472 protected pcmcia v cc and vpp switching matrix the ltc ? 1472 switching matrix routes power to both the v cc and vpp power supply pins of the pcmcia compatible card socket. the v cc output of the ltc1472 is switched between three operating states: off, 3.3v, and 5v. the vpp output is switched between four operating states: 0v, v cc , 12v, and hi-z. the output voltages are selected by two sets of digital inputs which are compatible with industry standard pc card controllers (see truth tables). the v cc output of the ltc1472 can supply up to 1a of current and the vpp output up to 120ma. both switches have built-in safeslot tm current limiting and thermal shut- down to protect the card, socket and power supply against accidental short-circuit conditions. the ltc1472 is designed to conserve power by automati- cally dropping to 1 m a standby current when the two outputs are switched off. a shutdown pin is provided which holds the external 12v regulator in standby mode except when required for vpp power. the ltc1472 is available in 16-pin so. descriptio n u features n both v cc and vpp switching in a single package n built-in current limit and thermal shutdown n 16-pin (narrow) soic package n inrush current limited (drives 150 m f loads) n continuous 12v power not required n extremely low r ds(on) nmos switches n guaranteed 1a v cc current and 120ma vpp current n 1 m a quiescent current in standby n no external components required n compatible with industry standard controllers n break-before-make switching n controlled rise and fall times applicatio n s u n notebook computers n palmtop computers n pen-based computers n handi-terminals n bar-code readers typical applicatio n u 3v in vpp in 5v in v dd vpp en0 vpp en1 v cc en0 v cc en1 shdn vpp out v cc(in) v cc(out) ltc1472 gnd 12v 3.3v 5v ov, v cc , 12v, hi-z vpp1 vpp2 v cc v cc pcmcia card slot controller pcmcia card slot off, 3.3v, 5v ltc1472-ta01 1 m f 0.1 m f 0.1 m f 10k 0.1 m f 0.1 m f to 12v regulator + device description package lt ? 1312 single pcmcia vpp driver/regulator 8-pin so lt1313 dual pcmcia vpp driver/regulator 16-pin so* ltc1314 single pcmcia switch matrix 14-pin so ltc1315 dual pcmcia switch matrix 24-pin ssop ltc1470 protected v cc 5v/3.3v switch matrix 8-pin so ltc1471 dual protected v cc 5v/3.3v switch matrix 16-pin so* ltc1472 protected v cc and vpp switch matrix 16-pin so* *narrow body protected pcmcia v cc and vpp card driver linear technology pcmcia product family , ltc and lt are registered trademarks of linear technology corporation. safeslot is a trademark of linear technology corporation.
2 ltc1472 absolute m axi m u m ratings w ww u 5v in supply voltage ................................... C 0.3v to 7v 3v in supply voltage ................................... C 0.3v to 7v vpp in supply voltage ............................ C 0.3v to 13.2v v cc(in) supply voltage ................................... C 0.3 to 7v v dd(in) supply voltage ............................... C 0.3v to 7v vpp out (off) ........................................ C 0.3v to 13.2v v cc(out) (off) ............................................ C 0.3v to 7v enable inputs .............................................. C 0.3v to 7v vpp out short-circuit duration ........................ indefinite v cc(out) short-circuit duration ....................... indefinite operating temperature range ..................... 0 c to 70 c junction temperature........................................... 100 c storage temperature range ................. C 65 c to 150 c lead temperature (soldering, 10 sec).................. 300 c order part number LTC1472CS consult factory for industrial and military grade parts. symbol parameter conditions min typ max units 5v in 5v in supply voltage range (note 2) 4.75 5.25 v 3v in 3v in supply voltage range (note 3) 0 3.60 v i 5vin 5v in supply current program to hi-z l 0.01 10 m a program to 5v, no load l 140 200 m a program to 3.3v, no load l 100 160 m a i 3vin 3v in supply current program to hi-z. l 0.01 10 m a program to 5v, no load l 0.01 10 m a program to 3.3v, no load l 40 80 m a r on 5v switch on resistance program to 5v, i out = 500ma 0.14 0.18 w 3.3v switch on resistance program to 3.3v, i out = 500ma 0.12 0.16 w i lkg output leakage current off v cc en0 = v cc en1 = 0v or 5v, 0v v cc(out) 5v l 10 m a i lim5v v cc(out) 5v current limit program to 5v, v cc(out) = 0v (note 4) 1 a i lim3v v cc(out) 3.3v current limit program to 3.3v, v cc(out) = 0v (note 4) 1 a v ccenh v cc enable input high voltage l 2v v ccenl v cc enable input low voltage l 0.8 v i vccen v cc enable input current 0v v ccen 5v l 1 m a t vcc1 delay + rise time from 0v to 3.3v, r load = 100 w , c load = 1 m f (note 5) 0.2 0.32 1 ms t vcc2 delay + rise time from 3.3v to 5v, r load = 100 w , c load = 1 m f (note 5) 0.2 0.52 1 ms t vcc3 delay + rise time from 0v to 5v, r load = 100 w , c load = 1 m f (note 5) 0.2 0.38 1 ms (v cc switch section) 5v in = 5v, 3v in = 3.3v, vpp en0 = vpp en1 = ov, t a = 25 c, (note 1) unless otherwise noted. electrical characteristics top view s package 16-lead plastic so t jmax = 100 c, q ja = 100 c/w 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 v cc(out) 5v in v cc en1 v cc en0 vpp in shdn vpp en0 vpp en1 v cc(out) 3v in 3v in gnd v cc(in) vpp out gnd v dd package/order i n for m atio n w u u
3 ltc1472 v dd = 5v, v cc(in) = 5v, vpp in = 12v, v ccen0 = v ccen1 = 0v, t a = 25 c, (note 1), unless otherwise noted. the l denotes the specifications which apply over the full operating temperature range. note 1: v enh = 5v, v enl = 0v. see v cc and vpp switch truth tables for programming enable inputs for desired output states. note 2: power for the v cc input logic and charge pump circuitry is derived from the 5v in power supply which must be continuously powered. 12v and 3.3v power is not required to control the nmos v cc switches. (see applications information.) note 3: the two 3v in supply input pins (14 and 15) must be connected together and the two v cc(out) output pins (1 and 16) must be connected together. the 3v in supply pins do not need to be continuously powered and may drop to 0v when not required. note 4: the v cc and vpp output are protected with foldback current limit which reduces the short-circuit (0v) currents below peak permissible current levels at higher output voltages. note 5: to 90% of final value. note 6: 12v power is only required when vpp out is programmed to 12v. the external 12v regulator can be shutdown at all other times. built-in charge pumps power the internal nmos switches from the 5v v dd supply when 12v is not present. note 7: power for the vpp input logic and charge pump circuitry is derived from the v dd power supply which must be continuously powered. note 8: to 90% of the final value, c out = 0.1 m f, r out = 2.9k. note 9: to 10% of the final value, c out = 0.1 m f, r out = 2.9k. note 10: to 50% of the initial value, c out = 0.1 m f, r out = 2.9k. electrical characteristics (vpp switch section) symbol parameter conditions min typ max units v cc(in) v cc input voltage range l 3 5.5 v vpp in vpp input voltage range (note 6) l 0 12.6 v v dd logic supply voltage range (note 7) l 4.5 5.5 v i ccin v cc(in) supply current, no load program to vpp in or v cc(in) vpp in = 12v l 35 60 m a program to 0v or hi-z l 0.01 10 m a i ppin vpp in supply current, no load program to vpp in or v cc(in) l 40 80 m a program to 0v or hi-z l 0.01 10 m a i dd v dd supply current, no load program to vpp in l 70 120 m a program to v cc(in) , vpp in = 0v l 85 150 m a program to v cc(in) , vpp in = 12v l 40 80 m a program to 0v or hi-z l 0.01 10 m a i vppout hi-z output leakage current program to hi-z, 0v < vpp out < 12v l 0.01 10 m a r on on resistance vpp out to vpp in vpp in = 12v, i load = 120ma 0.50 1 w on resistance vpp out to v cc(in) v cc(in) = 5v, i load = 5ma 1.70 5 w on resistance vpp out to gnd v dd = 5v, i sink = 1ma 100 250 w vpp enh vpp enable input high voltage v dd = 5v l 2v vpp enl vpp enable input low voltage v dd = 5v l 0.8 v i vppen vpp enable input current 0v < vpp en < vdd l 1 m a v sdh shdn output high voltage program to 0v, v cc(in) or hi-z, i load = 400 m a l 3.5 v v sdl shdn output low voltage program to vpp in , i sink = 400 m a l 0.4 v i limvcc vpp out current limit, v cc(in) program to v cc(in) , vpp out = 0v (note 4) 60 ma i limvpp vpp out current limit, vpp in program to vpp in , vpp out = 0v (note 4) 100 ma t vpp1 delay and rise time from 0v to v cc(in) ,vpp in = 0v (note 8) 5 15 50 m s t vpp2 delay and rise time from 0v to vpp in (note 8) 25 85 250 m s t vpp3 delay and rise time from v cc(in) to vpp in (note 8) 30 100 300 m s t vpp4 delay and fall time from vpp in to v cc(in) (note 9) 5 15 50 m s t vpp5 delay and fall time from vpp in to 0v (note 10) 10 35 100 m s t vpp6 delay and fall time from v cc(in) to 0v, vpp in = 0v (note 10) 10 30 100 m s t vpp7 output turn-on delay from hi-z to v cc(in) (note 8) 5 15 50 m s t vpp8 output turn-on delay from hi-z to vpp in (note 8) 25 85 250 m s
4 ltc1472 typical perfor m a n ce characteristics u w 5v in supply current (5v on) 5v in supply current (3.3v on) 5v switch resistance 3v in supply current (3.3v on) 3v in supply current (off) 3.3v switch resistance inrush current (3.3v switch) inrush current (5v switch) 5v in supply current (off) 5v in supply voltage (v) 0 ? 5v in supply current ( m a) 0 1 2 3 5 1 234 ltc1472 tpc01 56 4 t a = 25? v cc(out) programmed to off 5v in supply voltage (v) 0 0 5v in supply current ( m a) 50 100 150 200 300 1 234 ltc1472 tpc02 56 250 t a = 25? v cc(out) programmed to 5v, no load 3v in supply voltage (v) 0 ? 3v in supply current ( m a) 0 1 2 3 12 3 4 ltc1472 tpc04 4 5 t a = 25? output programmed to off 3v in supply voltage (v) 0 0 3v in supply current ( m a) 20 40 60 80 12 3 4 ltc1472 tpc05 100 120 t a = 25? v cc(out) programmed to 3.3v, no load time (ms) 0.2 inrush current (a) output voltage (v) 0 1 1.4 ltc1472 tpc09 6 4 0 0.2 0.6 1.0 2 3 2 0 0.4 0.8 1.2 c out = 150 m f r out = 6.6 w c out = 150 m f r out = 6.6 w c out = 15 m f r out = 6.6 w t j = 25? junction temperature (?) 0 0 3.3v switch resistance ( w ) 0.05 0.10 0.15 0.20 0.25 0.30 25 50 75 100 lt1472 tpc07 125 v cc(out) programmed to 3.3v time (ms) 0.2 inrush current (a) output voltage (v) 0 1 1.4 ltc1472 tpc08 6 4 0 0.2 0.6 1.0 2 3 2 0 0.4 0.8 1.2 c out = 150 m f r out = 10 w c out = 15 m f r out = 10 w t j = 25? current limited 5v in supply voltage (v) 0 0 5v in supply current ( m a) 50 100 150 200 300 1 234 ltc1472 tpc03 56 250 t a = 25? v cc(out) programmed to 3.3v, no load junction temperature (?) 0 0 5v switch resistance ( w ) 0.05 0.10 0.15 0.20 0.25 0.30 25 50 75 100 lt1472 tpc06 125 v cc(out) programmed to 5v (v cc section) vpp en0 = vpp en1 = 0v
5 ltc1472 vpp in supply voltage 0 vpp in supply current ( m a) 80 100 120 610 ltc1472 tpc12 60 40 24 81214 20 0 t a = 25? vpp in = 12v no load vpp out programmed to v cc(in) vpp out programmed to vpp in typical perfor m a n ce characteristics u w vpp in supply voltage 0 vpp in supply current ( m a) 3 4 5 610 ltc1472 tpc11 2 1 24 81214 0 ? t a = 25? vpp out programmed to 0v or hi-z v cc(in) supply current (no load) vpp in supply current (off) vpp in supply current (no load) v dd supply current (on) v cc(in) supply voltage (v) 0 ?0 v cc(in) supply current ( m a) 0 20 40 60 100 1 234 ltc1472 tpc10 56 80 vpp out programmed to 0v or hi-z vpp out programmed to vpp in or v cc(in) t a = 25? v dd supply current (off) v dd supply current (no load) (vpp section) v cc en0 = v cc en1 = 0v v dd supply voltage (v) 0 ? v dd supply current ( m a) 0 1 2 3 5 1 234 ltc1472 tpc13 56 4 t a = 25? vpp out programmed to 0v or hi-z v dd supply voltage (v) 0 0 v dd supply current ( m a) 20 40 60 80 120 1 234 ltc1472 tpc14 56 100 t a = 25? vpp out programmed to vpp in , no load v dd supply voltage (v) 0 0 v dd supply current ( m a) 20 40 60 80 120 1 234 ltc1472 tpc15 56 100 t a = 25? vpp out programmed to vpp in , no load vpp in = 0v vpp in = 12v switch resistances temperature (?) 020406080 0.1 switch resistance ( w ) 1 100 ltc1472 tpc16 10 vcc in to vpp out vpp in to vpp out
6 ltc1472 pi n fu n ctio n s uuu enable input (pins 3,4,7,8) the two v cc and two vpp enable inputs are designed to interface directly with industry standard pcmcia control- lers. they are high impedance cmos gates with esd protection diodes to ground, and should not be forced below ground. both sets of inputs have about 100mv of built-in hysteresis to ensure clean switching between operating modes. shutdown output (pin 6) the ltc1472 is designed to operate without continuous 12v power. the gates of the v cc nmos switches are powered by charge pumps from the 5v in supply, and the gates of the vpp nmos switches are powered by charge pumps powered from the v dd supply when 12v is not present at the vpp in pin (see application information for more details). therefore, the external 12v regulator can be shut down most of the time, and only turned on when programming the socket vpp pin to 12v. the shutdown output is active high; i.e. the system 12v regulator is shut down when this output is held high and turned on when this output is held low. vpp in supply (pin 5) the vpp in supply pin serves two purposes. the first purpose is to provide power and gate drive for the vpp in - vpp out switch. the second purpose is to provide optional 12v gate drive for the v cc(in) -vpp out switch. if, however, this 12v power is not available, gate drive is obtained automatically from the 5v v dd supply by an internal 5v to 12v charge pump converter. v dd supply (pin 9) the v dd pin provides power for the input, charge pump and control circuitry for the vpp section of the ltc1472 and therefore must be continuously powered. the standby quiescent current is typically 0.1 m a when the vpp out pin is programmed to 0v or hi-z and only rises to micropower levels when the vpp switches are active. v cc(in) supply (pin 12) the v cc(in) supply pin is typically connected directly to the v cc(out) pin from the v cc switch section of the ltc1472. it can also be connected directly to a 3.3v or 5v power supply if desired. this supply pin does not provide any power to the internal control circuitry and is simply the input to the v cc(in) -vpp out switch and therefore does not consume any power when unloaded or turned off. 5v in supply (pin 2) the 5v in supply pin serves two purposes. the first pur- pose is as the power supply input for the 5v nmos switch. the second purpose is to provide power for the input, gate drive and protection circuitry for both the 3.3v and 5v v cc switches, this pin must be continuously powered . the enable inputs should be turned off (both asserted high or both asserted low) at least 100 m s before the 5v in power is removed to ensure that both v cc nmos switch gates are fully discharged and both switches are in the high imped- ance mode. 3v in supply (pins 14,15) the 3v in supply pin serves as the power supply input for the 3.3v switch. this pin does not provide any power to the internal control circuitry and therefore does not consume any power when unloaded or turned off. v cc(out) and vpp out output (pins 1,11,16) the v cc output of the ltc1472 is switched between the three operating states: off, 3.3v, and 5v. the vpp output is switched between four operating states: 0, v cc , 12v and hi-z. both pins are protected against accidental short- circuit conditions to ground by independent safeslot foldback current-limit circuitry which protects the socket, card and the system power supplies against damage. a second level of protection is provided by independent thermal shut down circuitry which protects each switch against overtemperature conditions.
7 ltc1472 block diagra m w ttl-to-cmos converter oscillator and bias gate charge and discharge control logic charge pump gate charge and discharge control logic current limit and thermal shutdown 5v in 0.14 w 0.12 w v cc(out) 3v in break-before- make switch and control ttl-to-cmos converter v cc en0 v cc en1 ltc1470-bd01 vpp in vpp in vcc (in) vpp out 100 w 1.7 w 0.5 w 10v vpp en1 vpp en0 shdn v dd gate charge and discharge control logic oscillator and bias current limit and thermal shutdown charge pump gate charge and discharge control logic charge pump break-before- make switch ttl-to-cmos converter ttl-to-cmos converter + operatio n u the ltc1472 protected switch matrix is designed to be a complete single slot solution for v cc and vpp switching in a pcmcia compatible card system. the ltc1472 consists of two independent functional sections: the v cc switching section, and the vpp switching section. the v cc switching section the v cc switching section of the ltc1472 consist of the following functional blocks: v cc switch input ttl-cmos converters the ltc1472 v cc inputs are designed to accommodate a wide range of 3v and 5v logic families. the input threshold voltage is approximately 1.4v with approximately 100mv of hysteresis. the inputs enable the bias generator, the gate charge pumps and the protection circuity which are powered from the 5v in supply. therefore, when the inputs are turned off, the entire circuit is powered down and the 5v in supply current drops below 1 m a.
8 ltc1472 operatio n u to ground. both switches also have independent thermal shutdown which limits the power dissipation to safe levels. v cc xor input circuitry the ltc1472 ensures that the 3.3v and 5v switches are never turned on at the same time by employing an xor function which locks out the 3.3v switch when the 5v switch is turned on, and locks out the 5v switch when the 3.3v switch is turned on. this xor function also makes it possible for the ltc1472 to work with either active-low or active-high pcmcia v cc switch control logic (see applica- tions information for further details). v cc break-before-make switch control the ltc1472 has built-in delays to ensure that the 3.3v and 5v switch are non-overlapping. further, the gate charge pumps include circuity which ramps the nmos switches on slowly (400 m s typical rise time) but turn off much more quickly (typically 10 m s). v cc bias, oscillator and gate charge pump when either the 3.3v or 5v switch is enabled, a bias current generator and high frequency oscillator are turned on. an on-chip capacitive charge pump generates ap- proximately 12v of gate drive for the internal low r ds(on) nmos v cc switches from the 5v in power supply. there- fore, an external 12v supply is not required to switch the v cc output. the 5v in supply current drops below 1 m a when both switches are turned off. v cc gate charge and discharge control both v cc switches are designed to ramp on slowly (400 m s typical rise time). turn off time is much quicker (typically 10 m s). to ensure that both v cc nmos switch gates are fully discharged, program the switch to the high impedance mode at least 100 m s before turning off the 5v in power supply. v cc switch protection two levels of protection are designed into each of the power switches in the ltc1472. both v cc switches are protected against accidental short circuits with safeslot fold-back current limit circuits which limit the output current to typically 1a when the v cc(out) output is shorted the vpp switching section the vpp switching section of the ltc1472 consists of the following functional blocks: vpp switch input ttl-cmos converters the vpp inputs are designed to accommodate a wide range of 3v and 5v logic families. the input threshold voltage is 1.4v with ? 100mv of hysteresis. the inputs enable the bias generator, the gate charge pumps and the protection circuitry. when the inputs are turned off, the entire circuit is powered down and the v dd and vpp in supply currents drop below 1 m a. vpp break-before-make switch control the vpp input section has built-in delays to ensure that the vpp switchs are non-overlapping. further, the gate charge pumps include circuitry which ramps the nmos switches on slowly but turns them off quickly. vpp bias, oscillator and gate charge pump when either the vpp in -vpp out or v cc(in) -vpp out switch is enabled, a bias current generator and high frequency oscillator are turned on. an on-chip capacitive charge pump generates approximately 23v of gate drive for the internal low r ds(on) nmos vpp in -vpp out switch from the vpp in power supply. the gate of the v cc(in) -vpp out nmos switch is either powered by the external 12v regulator (if left on) or automatically from a built-in charge pump powered from the v dd supply when the external 12v supply drops below 10v. the v dd supply current drops below 1 m a when switched to either the 0v or hi-z mode. v cc en0 v cc en1 v cc(out) 0 0 off 105v 0 1 3.3v 1 1 off v cc switch truth table
9 ltc1472 vpp gate charge and discharge control the vpp switches are designed to ramp slowly (typically tens of m s) between output modes to reduce supply glitching when powering large capacitive loads. vpp switch protection both vpp power switches are protected against accidental short circuits with safeslot fold-back current limit circuits which limit the short-circuit (0v) output current to typi- operatio n u applicatio n s i n for m atio n wu u u cally 100ma when protecting the 12v vpp in supply and 60ma when protecting the v cc(in) supply. (higher operat- ing currents are allowed at higher output voltages). both switches also have thermal shutdown. vpp switch truth table vpp en0 vpp en1 vpp out 000v 01v cc(in) 1 0 vpp in 1 1 hi-z the ltc1472 is a complete single slot v cc and vpp power supply switch matrix with safeslot current limit protection on both outputs. it is designed to interface directly with industry standard pcmcia card controllers and to indus- try standard 12v regulators. interfacing to the cl-pd6710 and the lt ? 1301 figure 1 shows the ltc1472 interfaced to a standard pcmcia slot controller and an lt1301 step-up switching regulator. the ltc1472 accepts logic control directly from the cl-pd6710 and in turn, controls the lt1301 to provide clean 12v vpp programming power when re- quired. the lt1301 is then shutdown (10 m a standby current) at all other times to conserve power. the xor v cc input function allows the ltc1472 to inter- face directly to the active-low v cc control outputs of the cl-pd6710 for 3.3v/5v voltage selection (see the v cc switch truth table). therefore, no glue logic is required to interface to this pcmcia compatible controller. the ltc1472 provides safeslot current-limit protection for the lt1301 step-up regulator, the system 3.3v and 5v regulators, the socket and the card. further, depending upon the system regulators own current limits, it may allow the system power supplies to continue operation during a card/slot short circuit without losing data, etc. 3v in 3v in shdn 5v in v dd vpp en0 vpp en1 v cc en0 v cc en1 vpp in vpp out v cc(in) v cc(out) v cc(out) gnd gnd ltc1472 v in sel shdn pgnd sw sense i lim gnd lt1301 3.3v 0.1 m f 5v 5v 0.1 m f cl-pd6710 vpp_v cc vpp_pgm v cc _3 v cc _5 pcmcia card slot vpp1 vpp2 v cc v cc 0.1 m f 10k 1 m f tant off, 3.3v, 5v 0.1 m f 0.1 m f 47 m f 16v tant (12v) 100 m f 10v 10 m h coilcraft do1608-103 3 2 10k + + + 6 7 4 5 nc mbrs130lt3 0v, v cc , 12v, hi-z 1 8 ltc1472-f01 figure 1. direct interface to industry standard pcmcia controller and lt1301 step-up switching regulator
10 ltc1472 applicatio n s i n for m atio n wu u u interfacing to 365 type controllers the ltc1472 also interfaces directly with 365 type controllers as shown in figure 2. the v cc enable inputs are connected differently than to the cl-pd6710 control- ler because the 365 type controllers use active-high logic control of the v cc switches (see the v cc switch truth table). no glue logic is required to interface to this type of pcmcia compatible controller. 12v power requirements note that in figure 2, a local 5v to 12v converter is not used. the ltc1472 works equally well with or without continuous 12v power. if the main power supply system has 12v continuously available, simply connect it to the vpp in pin. internal circuitry automatically senses its pres- ence and uses it to switch the internal vpp switches. the 12v shutdown output can be used to shut down the system 12v power supply (if not required for any purpose other than vpp programming). 5v power requirements the ltc1472 has been designed to operate without con- tinuous 12v power, but continuous 5v power is required at the v dd and 5v in supply pins for proper operation and should always be present when a card is powered (whether it is a 5v or 3.3v only card). if the 5v power must be turned off, for example, to enter a 3.3v only full system sleep mode, the 5v supply must be turned off at least 100 m s after the v cc and vpp switches have been programmed to the hi-z or 0v states. this ensures that the gates of the nmos switches are com- pletely discharged. also, the v cc switches cannot be operated properly with- out 5v power. they must be programmed to the off state at least 100 m s prior to turning the 5v supply off, or they may be left in an indeterminate state. supply bypassing for best results, bypass the supply input pins with 1 m f capacitors as close as possible to the ltc1472. some- times, much larger capacitors are already available at the outputs of the 3.3v, 5v and 12v power supply. in this case, it is still good practice to use 0.1 m f capacitors as close as possible to the ltc1472, especially if the power supply output capacitors are more than 2" away on the printed circuit board. 3v in 3v in shdn 5v in v dd vpp en0 vpp en1 v cc en0 v cc en1 vpp in vpp out v cc(in) v cc(out) v cc(out) gnd gnd ltc1472 3.3v 0.1 m f 5v ?65?ype controller a_vpp_en0 a_vpp_en1 a_v cc _en0 a_v cc _en1 pcmcia card slot vpp1 vpp2 v cc v cc 10k 1 m f tant (off, 3.3v, 5v) 10k + 0.1 m f 0.1 m f (0v, v cc , 12v, hi-z) ltc1472-f02 12v shutdown (optional) 12v figure 2. direct interface to industry standard pcmcia controller and lt1301 step-up switching regulator
11 ltc1472 applicatio n s i n for m atio n wu u u output capacitors the v cc(out) pin is designed to ramp on slowly, typically 400 m s rise time. therefore, capacitors as large as 150 m f can be driven without producing voltage spikes on the 5v in or 3v in supply pins (see graphs in typical perfor- mance characteristics). the v cc(out) pin should have a 0.1 m f to 1 m f capacitor for noise reduction and smoothing. the vpp out pin should have a 0.01 m f to 0.1 m f capacitor for noise reduction. the vpp in capacitors should be at least equal to the vpp out capacitors to ensure smooth transitions between output voltages without creating spikes on the system power supply lines. supply sequencing because the 5v supply is the source of power for both the v cc and vpp switch control logic, it is best to sequence the power supplies such that the 5v supply is powered before or simultaneous to the application of 3.3v or 12v power. it is interesting to note however, that all of the switches in the ltc1472 are nmos transistors which require charge pumps to generate gate voltages higher than the supply rails for full enhancement. because the gate voltages start a 0v when the supplies are first activated, the switches always start in the off state and do not produce glitches at the output when powered. some pcmcia switch matrix products employ pmos switches for 12v vpp control and great care must be taken to ensure that the 5v control logic is powered before the 12v supply is turned on. if this sequence is not followed, the pmos vpp switch gate may start at ground potential and the vpp output may be inadvertently forced to 12v. although, not advisable, it is possible to power the 12v vpp in supply pin of the ltc1472 prior to application of 5v power. only about 50 m a flows to the vpp out pin under these conditions. if the 5v supply must be turned off, it is important to program all switches to the hi-z or 0v state at least 100 m s before the 5v power is removed to ensure that all nmos switch gates are fully discharged to 0v. whenever possible however, it is best to leave the 5v in and v dd pins continuously powered. the ltc1472 quiescent current drops to < 1 m a with all the switches turned off and therefore no 5v power is consumed in the standby mode.
12 ltc1472 typical applicatio n s u dual protected pcmcia power management system 3v in 3v in shdn 5v in v dd vpp en0 vpp en1 v cc en0 v cc en1 vpp in vpp out v cc(in) v cc(out) v cc(out) gnd gnd ltc1472 v in sel shdn pgnd sw sense i lim gnd lt1301 3.3v 0.1 m f 3.3v or 5v 5v 0.1 m f pcmcia card slot vpp1 vpp2 v cc v cc 0.1 m f 10k 1 m f tant off, 3.3v, 5v 0.1 m f 0.1 m f 47 m f 16v tant 12v 100 m f 10v 33 m h* coilcraft do3316-333 3 2 10k + + + 6 7 4 5 nc mbrs130lt3 0v, v cc , 12v, hi-z 1 8 ltc1472-ta02 3v in 3v in shdn 5v in v dd vpp en0 vpp en1 v cc en0 v cc en1 vpp in vpp out v cc(in) v cc(out) v cc(out) gnd gnd ltc1472 3.3v 0.1 m f 5v 0.1 m f b_vpp_v cc b_vpp_pgm b_v cc _3 b_v cc _5 pcmcia card slot vpp1 vpp2 v cc v cc 0.1 m f 10k 1 m f tant off, 3.3v, 5v 10k + 0.1 m f 0v, v cc , 12v, hi-z cl-pd6720 a_vpp_v cc a_vpp_pgm a_v cc _3 a_v cc _5 *for 5v to 12v conversion use 10 m h, coilcraft do1608-103. see lt1301 data sheet for more detailed information on inductor and capacitor selection.
13 ltc1472 typical applicatio n s u single protected pcmcia power management system using the lt1301 powered from 3.3v or 5v 3v in 3v in shdn 5v in v dd vpp en0 vpp en1 v cc en0 v cc en1 vpp in vpp out v cc(in) v cc(out) v cc(out) gnd gnd ltc1472 v in sel shdn pgnd sw sense i lim gnd lt1301 3.3v 0.1 m f 3.3v or 5v 5v 0.1 m f cl-pd6710 vpp_v cc vpp_pgm v cc _3 v cc _5 pcmcia card slot vpp1 vpp2 v cc v cc 0.1 m f 10k 1 m f tant off, 3.3v, 5v 0.1 m f 0.1 m f 47 m f 16v tant 12v 100 m f 10v 33 m h* coilcraft do3316-333 3 2 10k + + + 6 7 4 5 nc mbrs130lt3 0v, v cc , 12v, hi-z 1 8 ltc1472 ta03 *for 5v to 12v conversion use 10 m h, coilcraft d01608-103. see lt1301 data sheet for more detailed information on induction and capacitor selection.
14 ltc1472 typical applicatio n s u single protected pcmcia power management system using the lt1121 powered from an auxiliary winding for 12v vpp power 1 m f tant 12v 121k 200pf 56.2k 2n7002 + 3v in 3v in shdn 5v in v dd vpp en0 vpp en1 v cc en0 v cc en1 vpp in vpp out v cc(in) v cc(out) v cc(out) gnd gnd ltc1472 in shdn pgnd out adj gnd lt1121cs8 3.3v 0.1 m f 5v 0.1 m f cl-pd6710 vpp_v cc vpp_pgm v cc _3 v cc _5 pcmcia card slot vpp1 vpp2 v cc v cc 0.1 m f 10k 1 m f tant off, 3.3v, 5v 10 m f 10v 5 + + 0.1 m f 8 1 2 0v, v cc , 12v, hi-z 3 6, 7 ltc1472 ta04 *see the ltc1142 data sheet for an example of a 3.3v/5v dual regulator with auxiliary winding 15v output 100k 5v *13v to 20v (may be from auxiliary winding)
15 ltc1472 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of circuits as described herein will not infringe on existing patent rights. typical applicatio n s u dual protected pcmcia power management system powered by system 12v supply 3v in 3v in shdn 5v in v dd vpp en0 vpp en1 v cc en0 v cc en1 vpp in vpp out v cc(in) v cc(out) v cc(out) gnd gnd ltc1472 3.3v 12v 0.1 m f 5v 0.1 m f cl-pd6720 b_vpp_v cc b_vpp_pgm b_v cc _3 b_v cc _5 pcmcia card slot vpp1 vpp2 v cc v cc 0.1 m f 10k 1 m f tant off, 3.3v, 5v + 0.1 m f 0v, v cc , 12v, hi-z ltc1472 ta05 nc 3v in 3v in shdn 5v in v dd vpp en0 vpp en1 v cc en0 v cc en1 vpp in vpp out v cc(in) v cc(out) v cc(out) gnd gnd ltc1472 3.3v 12v 0.1 m f 5v 0.1 m f a_vpp_v cc a_vpp_pgm a_v cc _3 a_v cc _5 pcmcia card slot vpp1 vpp2 v cc v cc 0.1 m f 10k 1 m f tant off, 3.3v, 5v + 0.1 m f 0v, v cc , 12v, hi-z nc
16 ltc1472 lt/gp 0395 10k ? printed in usa ? linear technology corporation 1995 package descriptio n u linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7487 (408) 432-1900 l fax : (408) 434-0507 l telex : 499-3977 dimensions in inches (millimeters) unless otherwise noted. s-package 16-lead plastic soic 0.016 ?0.050 0.406 ?1.270 0.010 ?0.020 (0.254 ?0.508) 45 0 ?8 typ 0.008 ?0.010 (0.203 ?0.254) 1 2 3 4 5 6 7 8 0.150 ?0.157* (3.810 ?3.988) 16 15 14 13 0.386 ?0.394* (9.804 ?10.008) 0.228 ?0.244 (5.791 ?6.197) 12 11 10 9 so16 0893 0.053 ?0.069 (1.346 ?1.752) 0.014 ?0.019 (0.355 ?0.483) 0.004 ?0.010 (0.101 ?0.254) 0.050 (1.270) typ *these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.006 inch (0.15mm). related parts see pcmcia product family table on the first page of this data sheet.

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